In preparation for the Work Programme for 2027, Chips JU is organising an online consultation workshop on the 6th of October 2026. The workshop will focus on the broader theme of Chips for AI, AI for Chips. It will bring together stakeholders from across the Electronic Components and Systems community to discuss ideas for potential Calls 2027 topics, exchange views on industrial needs and technology priorities, inform and help refine the direction of future Chips JU actions. The workshop is organised around three complementary areas: adaptive and autonomous systems across their full lifecycle, AI-driven chip design, and system-level memory architectures for AI. Input gathered at the workshop will feed into the drafting of the Chips JU Work Programme 2027 and its call topics.
To kickstart the discussion, draft topic concepts have been prepared with contributions from experts in the field. Participants will have the opportunity provide feedback on draft concepts’ relevance and ambition, share new ideas, and help identify the most important gaps and opportunities for Europe in the field.
The workshop will be structured around three sessions.
Tentative time: 9:00 – 11:00
This session will address the semiconductor foundations needed to enable adaptation and autonomy over the full system lifecycle, with a focus on key technical challenges across sensing, heterogeneous compute, AI, trust and safety, scalability, and system-level autonomy. It will bring together two closely linked topic areas:
Together, these topics will address opportunities in application domains such as automotive, humanoid robotics, healthcare and industrial applications, helping to strengthen European leadership in trustworthy, adaptive and semiconductor-enabled autonomous systems.
Tentative time: 11:15-13:00
This session will address the potential of AI-driven EDA tools and methodologies for the design, verification and optimisation of advanced semiconductor components and systems. It will tackle how machine learning and generative AI can help shorten design cycles, reduce costs and lower entry barriers for European fabless companies, SMEs and research organisations. The session will also consider how such capabilities can strengthen European sovereignty in chip design and support the development of design technologies for the next generation of AI systems, including accessible tool flows, datasets and validated design cases.
Tentative time: 14:00-15:45
This session will focus on advanced memory architectures tailored to the demanding requirements of AI workloads. Areas of discussion include disaggregated memory systems, compute-near-memory integration, memory-centric SoC co-design, and software stacks for heterogeneous memory systems. The discussion will explore how these approaches can improve performance, energy efficiency, scalability and resource utilisation in AI systems, while reinforcing European capabilities in next-generation computing architectures and system integration.
