Join Consultation Workshop on Co-Packaged Optics and System-Level Design for Heterogeneous Integration!

Co-Packaged Optics for Advanced Data Communication

Co-packaged optics is becoming a key enabler of energy-efficient AI and HPC infrastructure, and Europe holds strong positions in several parts of the value chain, the workshop will focus on energy-efficient, high-throughput, low-latency datalinks. Among the potential applications are scale-up and scale-out interconnects within data centres, data centre interconnect (scale-across), and optical circuit switching. Many other applications can benefit from the developments pulled by AI needs. The workshop will touch amongst other on the topics of optical engine and transceiver integration, fibre-to-chip coupling, thermal management, test, and reliability qualification.

Experts from the field of integrated photonics, heterogeneous integration, and packaging will introduce the needs and identify directions where collaborative research can accelerate commercial developments of adequate co-packaged optics devices for the relevant applications. Participants will have the opportunity to provide feedback on the draft concepts’ relevance and ambition, share new ideas, and help identify the most important gaps and opportunities for innovation in Europe.

System-Level Design for Heterogeneous Integration

Current design methods and EDA tools are mature at the RTL level but struggle on the system level: early design stages offer little insight into whether an architecture can support future updates or product variants without costly redesigns.

Analogue and RF components are often integrated too late, leading to problems further down the line. Security and safety aspects, such as isolation, redundancy, and minimising attack surfaces, tend to be addressed reactively rather than by design, and there is still no unified way to weigh architecture choices against thermal, mechanical, and cost trade-offs early on.

Between now and 2030, closing this system-level gap is seen as a key lever for strengthening European technological sovereignty and competitiveness, alongside efforts to expand chip manufacturing capacity.

The proposed topic objective is the development of a new system-level design methodology that allows early, holistic evaluation of complex architectures, covering flexibility, security, and long-term adaptability from the outset. Scalable abstraction, from high-level exploration down to subsystem refinement, and full traceability from requirements to architectural decisions are equally essential.